Learning objectives
The course will first address the problem of fault modeling, with reference to the automotive environment, to then study testing, design testability and hardware in the loop approaches. Then, onboard monitoring and diagnosis will be addressed, to finally study fault tolerant techniques for reliable systems’ design. The course will include laboratory experiences, and possible seminars given by experts in the field from the industrial world.
Prerequisites
Basic concepts of digital electronics.
Course unit content
Effects of resistive bridging faults affecting the clock distribution of ICs implemented by scaled technologies.
Effects of crosstalk fault on the bus lines of ICs implemented by scaled technologies, and traditional techniques to mitigate the effects of crosstalk faults.
Generation of transient faults and soft errors in data-paths of ICs implemented by scaled technologies. Methodologies to increase the robustness of combinational circuits and memory elements.
Introduction to main degradation phenomena affecting ICs implemented by scaled technologies, and their impact on circuits’ reliability. Design approaches to mitigate the impact of degradation phenomena on circuits’ reliability.
Error Correcting Codes: Introduction to Linear Parity Check Codes; Single Error Correction Hamming Codes; Single Error Correction/Double Error Detection Hsiao Codes; Encoding and Decoding Circuits.
Introduction to Hardware-in-the-Loop testing technique.
The course includes practice sessions in laboratories on: Electrical level simulations of resistive bridging faults, crosstalk faults and transient faults, and analysis of their effects in some circuits of interest.
Full programme
Effects of resistive bridging faults affecting the clock distribution of ICs implemented by scaled technologies.
Effects of crosstalk fault on the bus lines of ICs implemented by scaled technologies, and traditional techniques to mitigate the effects of crosstalk faults.
Generation of transient faults and soft errors in data-paths of ICs implemented by scaled technologies. Methodologies to increase the robustness of combinational circuits and memory elements.
Introduction to main degradation phenomena affecting ICs implemented by scaled technologies, and their impact on circuits’ reliability. Design approaches to mitigate the impact of degradation phenomena on circuits’ reliability.
Error Correcting Codes: Introduction to Linear Parity Check Codes; Single Error Correction Hamming Codes; Single Error Correction/Double Error Detection Hsiao Codes; Encoding and Decoding Circuits.
Introduction to Hardware-in-the-Loop testing technique.
The course includes practice sessions in laboratories on: Electrical level simulations of resistive bridging faults, crosstalk faults and transient faults, and analysis of their effects in some circuits of interest.
Bibliography
J. Segura C. F. Hawkins, “CMOS Electronics – How It Works, How It Fails” IEEE Press – Wiley, 2004
M. L. Bushnell, V. D. Agrawal, “Essential of Electronic Testing”, Kluwer Academic Publishers, 2000
M. Abramovici, M. A. Bruer, A. D. Friedman, “Digital Systems Testing and Testable Design”, Computer Science Press, 1990
S. Mourad, Y. Zorian, “Principles of Testing Electronic Systems”, Essential of Electronic Testing”,Wiley, 2000
N. K. Jha, S. Kundu, “Testing and Reliable Design of CMOS Circuits” Kluwer Academic Publishers, 1990
P. K. Lala, “Self-Checking and Fault Tolerant Digital Design”, Morgan Caufmann Publ, 2001
Teaching methods
Lessons in the classroom and computer exercises performed laboratory.
Assessment methods and criteria
Oral examination. Questions will cover any topic addressed in class and in the laboratory. Specific questions may follow aimed at verifying the understanding of specific issues inherent to the topics covered in the course. The final grade will be formulated based on the answers provided to the asked questions.
Other information
Slides used during classes will be made available to the students. The course will include some seminars from industrial experts in the field.
