Learning objectives
_Learning objectives_
Course learning objectives are to provide students with knowledge and
understanding of fundamental techniques for digital system analysis and design. Both traditional methodologies suitable for paper and pencil and algorithmic techniques adopted in industrial Design Automation flows are presented. Emphasis is placed on the development of problem solving capabilities, including the ability to address design problems at high level by partitioning them into subproblems and exploiting the most appropriate components and techniques for individual subproblems.
At the end of the course, students will be able to directly apply the learned techniques in the following contexts:
- Analysis and design of small to medium combinational circuits using logic gates as well as LSI and MSI components;
- Analysis and design of small to medium synchronous sequential circuits using logic gates and flip-flops as well as functional modules such as registers, counters, memories;
- Interfacing digital systems with external signals using latches and flip-flops;
- Behavioral and structural approaches in the design of digital systems, taking into account cost and performance issues;
- Ability to use a problem solving approach to partition complex problems into manageable subproblems that can be individually tackled and solved.
Prerequisites
_Prerequisites_
Knowledge of fundamental gates, Boolean algebra and some basics of
combinational synthesis is assumed. Elementary techniques for combinational synthesis (K-maps, expression simplification) will be quickly recalled before delving into more advanced course topics.
Course unit content
_ Digital Design: Course short description_
- Models of digital circuits
- Recall of elementary techniques for analysis and synthesis of combinational circuits
- Integrated combinational circuits: SSI, MSI, LSI, programmable circuits (ROM, PLA, PAL, GAL, CPLD)
- Analysis and synthesis techniques for synchronous sequential circuits
- Bistable memory circuits
- Integrated sequential circuits: registers, counters, sequential programmable components, memory banks
- Analysis and synthesis techniques for complex digital systems
- Optional topic (if time permits): Analysis and synthesis techniques for asynchronous sequential circuits
Full programme
__Digital Design: Detailed Course Syllabus__
Introduction to digital systems
1 - The role of digital systems. Digital representation of information.
2 - Von Neumann's architecture.
3 - Evolution of electronic technologies.
4 - Objectives and limitations of digital systems.
Combinational logic design
1 - Review: Canonical and general logic expressions (SoP and PoS). Analysis and synthesis of fully specified logic functions based on Karnaugh maps.
2 - Other two-level logic analysis and synthesis techniques: Incompletely specified logic functions. Multiple output circuits. Analysis and synthesis of NAND and NOR circuits.
3 - Multilevel logic and integrated circuit-based design: Expression factorization and decomposition. Combinational logic design based on standard integrated circuits. SSI logic family. MSI and LSI parts (Multiplexers, Decoders, Demultiplexers, Encoders, ROMs, AOI components).
4 - Interconnection technologies: Three-state gates, buffers, tranceivers, busses. Three-state based MUX and DEMUX implementation.
5 - Combinational programmable logic (ROM, PLA, PAL, GAL).
6 - Transient phenomena in combinational circuits: static and dynamic hazards.
7 - CAD tools for combinational network design: Quine-McCluskey algorithm. Espresso. Logic simulation.
Synchronous sequential logic design
1 - Mealy and Moore machines. Elementary logic circuits with delays and feedback. Fundamental mode operation. Clocked operation.
2 - Basic memory elements: SR and D Latches; D, JK, and T Flip-Flops. Timing problems. Timing in synchronous circuits.
3 - Finite state automata: Automata description techniques (state diagram, flow table, description language). State minimization.
4. Analysis and synthesis of synchronous sequential circuits: State encoding. Optimal and one-hot encodings. State memory implementation with Flip-Flops and Latches.
5 - The synchronous/asynchronous interface: Flip-Flops with Preset and Clear commands. Management of asynchronous and pulsed inputs in synchronous circuits.
6 - Counters and Registers: Design of binary counters, ring counters, Johnson counters, counters with arbitrary state encoding. Parallel registers and shift registers. Control inputs in counters and registers.
7 - Sequential programmable logic (CPLD, FPGA).
Analysis and synthesis of complex digital systems
1 - Sequential circuit design using standard integrated circuits (registers, counters, shift-registers, sequencers, MUXes, etc.).
2 - Memory banks design.
3 - Complex circuit design by decomposition into datapath and control unit. Control unit design.
4 - Data path components and dedicated combinational components: Arithmetic circuits (adders, comparators, ALU). Transcoders. Parity and Hamming circuitry. XOR-based circuits.
5 - Design techniques for pipelined circuits.
6 (optional topic) - Hardware description languages.
Asynchronous sequential logic design
(Advanced topic, optional)
1 - State diagrams and state tables for asynchronous state machines.
2 - State minimization.
3 - State encoding. Prevention of criticale races. Prevention of functional hazards.
4 - State marking via direct feedback or latches.
5 - Asynchronous control units design.
Bibliography
_Textbooks_
Lecture notes and exercises with solutions are made available on the course web site to registered students.
For a comprehensive treatment of the subject please refer to the following textbooks, which the course draws inspiration from:
- F. Vahid, Digital Design, John Wiley & Sons, 2007.
- J.F. Wakerly, Digital Design: Principles and Practice, 4th Edition, Prentice-Hall, 2005.
Additional textbooks (to probe further specific subjects or to look for exercises):
- C. Bolchini, C. Brandolese, F. Salice, D. Sciuto, Reti Logiche, Apogeo, 2004.
-R.H. Katz, Contemporary Logic Design, 1st Edition, Addison Wesley, 1994.
- R. Laschi, Reti Logiche, Esculapio, Bologna, 1994.
The course covers a very classical computer engineering discipline. Hence, a number of textbooks dealing with the subject are available in the Engineering School Library, in Italian as well as in English.
Teaching methods
My plan is to deliver the entire course in a large classroom (room A/1 in the Scientific Building of Engineering), where the whole class can attend the lecture at the same time. All students will be able to stay at prescribed mutual in the class distance, but very likely they will have to wear face masks. Students must also use the seat reservation app.
In case of COVID-related issues (total or partial lockdown or class quarantine), some or all lectures will be delivered remotely via the Teams platform.
The course includes about 80 hours of supervised learning activity (lectures and excercises in classroom, and a few lectures with laboratory activity). Most of the course involves lectures and exercises in classroom using chalkboard, overhead projector, and/or computer slides as needed. A large fraction of lecture time is reserved for design activities, typically carried out on the main chalkboard to include design suggestions from the more lively students attending the class.
A 2-4 hour seminar in the lab may be proposed (COVID pandemic permitting) to overview digital design techniques with programmable logic components using industrial CAD tools (schematic entry, VHDL, digital simulation, project mapping on assigned programmable components).
During the semester, two midterms as well as a few exercise or theory home assignments are administered to keep students on pace with the course and exe with the course. Midterms will be held in mid-November and in December immediately after the end of the lecture period (i.e. before Chirstmas). If both midterms are passed, the average mark obtained will be proposed as final mark for the exam. In all other cases, the student will take the full exam in one of the official exam dates.
Assessment methods and criteria
_Course exam_
Recommended mode: Two written midterms at half and end of lecturing period.
Otherwise: Comprehensive written test during an official exam sessions.
Written tests (as well as midterms) always include exercises with design and analysis of several types of digital circuits, covering all the course topics. Written tests may also include one or few quizzes about more theory-oriented topics. More frequently, theory must be known and used to solve the proposed design problems.
Other information
Course web site available at: http://elly2020.dia.unipr.it for registered students.
Students must register to the course web site to receive all communications from the instructor.
Teaching material is published on the web site as course progresses.
2030 agenda goals for sustainable development
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