Learning objectives
The course objective is to introduce the basic techniques for analysis and design of synchronous digital systems. Both traditional methodologies and algorithmic techniques exploited in industrial Design Automation flows are presented.
Prerequisites
<br /> <br />Passing 'Fondamenti di informatica B' (Fundamentals of Computer Engineering B) before 'Reti logiche A' (Digital design) is highly recommended, although not formally enforced.
Course unit content
<br />Reti logiche A (Digital design) is a fundamental course.<br /> <br />Introduction to digital systems<br />Evolution of electronic technologies. Objectives and limitations of synchronous digital systems.<br /><br />Combinational logic design<br />1 - Review: Canonical and general logic expressions (SP and PS). Analysis and synthesis of fully specified logic functions based on Karnaugh maps.<br />2 - Other two-level logic analysis and synthesis techniques: Incompletely specified logic functions. Multiple output circuits (multiple prime implicants/implicates method). Analysis and synthesis of NAND and NOR circuits.<br />3 - CAD tools for combinational logic design: Quine-McCluskey algorithm. Espresso. Logic simulation.<br />4 - Multilevel logic and integrated circuit-based design: Expression factorization and decomposition. Combinational logic design based on standard MSI and LSI parts (Multiplexers, Decoders, Encoders, ROMs, AOI components).<br />5 - Programmable logic (PLA, PAL, GAL).<br />6 - Dedicated combinational circuits: Arithmetic circuits (adders, comparators, ALU). Transocoders. Parity and Hamming circuitry. XOR based circuits.<br />7 - Transient phenomena in combinational circuits: static and dynamic hazards.<br /><br />Synchronous sequential logic design<br />1 - Mealy and Moore machines. Elementary logic circuits with delays and feedback. Fundamental mode operation.<br />2 - Basic memory elements: SR and D Latches; D, JK, and T Flip-Flops. Timing issues. Timing in synchronous circuits.<br />3 - Finite state automata: Automata description techniques (state diagrams, flow tables, description languages). State minimization. <br />4. Analysis and synthesis of synchronous sequential circuits: State encoding. State memory implementation with Flip-Flops and Latches.<br />5 - The synchronous/asynchronous interface: Flip-Flops with Preset and Clear commands. Management of asynchronous and pulsed inputs in synchronous circuits.<br />6 - Counters and Registers: Design of binary counters, Johnson counters, counters with arbitrary state encoding. Parallel registers and shift registers. <br />7 - Sequential programmable logic (FPGA).<br /> <br />Analysis and synthesis of complex digital systems <br />1 - Sequential circuit design based on standard integrated circuits (registers, counters, shift-registers, sequencers, MUXes, etc.).<br />2 - Complex circuit design by decomposition in datapath and control unit.<br />3 - Design techniques for pipelined circuits.<br />4 - Hardware description languages.<br /><br /><br />Laboratory activities<br />Guided exercise solution in classroom will be routinely performed. In addition, laboratory sessions with simple CAD tools for logic design entry and digital simulation will be proposed.
Full programme
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Bibliography
<br />Lecture notes are available for download in the web site of the course (student registration is required for access to the web site).<br />M.M. Mano, Digital Design, 3/e, Prentice Hall, 2002. (In English).<br />C. Bolchini, C. Brandolese, F. Salice, D. Sciuto, Reti Logiche, Apogeo, 2004. (In Italian).<br />R. Katz, G. Borriello, Contemporary Logic Design, 2nd edition, Pearson, 2005. (In English).
Teaching methods
<br />The recommended exam modality is to undertake the two planned mid-term written tests during the teaching period. Alternatively, a single written test covering the whole course program must be passed in any of the scheduled official exam dates. Tests include both theory questions and design exercises.
Assessment methods and criteria
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Other information
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