Learning objectives
The course will first address the problem of fault modeling, with reference to the automotive environment, to then study testing, design for testability and hardware in the loop approaches. Then, onboard monitoring and diagnosis will be addressed, to finally study fault tolerant techniques for reliable systems’ design. The course will include laboratory experiences, and possible seminars given by experts in the field from the industrial world.
Course unit content
Introduction to Digital Circuit and Systems' Testing
Definitions and motivations
Position within the VLSI process
Yield and production cost of an IC
Some example of testing process: Characterization Testing; Manufacturing Testing; Burn-in; Incoming Inspection
Fault Models
Stuck-At Faults (SAs): Basics on Testing for SAs
Fault Equivalence and Fault Collapsing
Checkpoint Theorem
Fault Dominance and Fault Collapsing
Stuck-Open Faults: Possible Testing
Stuck-On Faults: Possible Testing
Bridging Faults, Delay Faulrts, Crosstalk Faults and Transient Faults: Possible Testing
Automatic Test Pattern Generation (ATPG)
Definition
ATPG Algebras
Exhaustive Algorithms
Random Algorithms
Path Sensitization
Fault Coverage and Test Efficiency
Automatic Test Equipment (ATE)
Components and Specification
Cost
Fault Diagnosis
Definitions and Motivations
Fault Dictionary
Diagnostic Tree
Design for Testability (DFT) Techniques and Hardware in the Loop Approaches
Introduction
Ad-Hoc and Structural Methods
Full Scan
Partial Scan
Boundary Scan
Built-In-Self Test (BIST)
Built-In-Logic-Block-Observer (BILBO)
Hardware in the loop approaches
Fault-Tolerant Techniques
Introduction: Motivations; Applications
Modular Redundancy: Basic Strategy; Voter Design and Reliability; Common Mode Failures; Diagnosis of Faulty Modules
On-Line Testing and Recovery: Duplication and Comparison; Self Checking Circuits
Self-Checking Circuits: Properties; Fault Hypothesis; Design of Self Checking Functional Blocks; Design of Checkers; Error Indicators
Error Detecting Codes: Berger Codes (Theory and Checker Design); Parity Codes (Theory and Checker Design); m-out-of-n Codes (Theory and Checker Design)
Recovery Techniques: Roll Back and Retry; Reconfiguration
Error Correcting Codes: Introduction to Linear Parity Check Codes; Single Error Correction Hamming Codes; Single Error Correction/Double Error Detection Hsiao Codes; Encoding and Decoding Circuits
The course includes practice sessions in laboratories on:
Electrical level simulations of resistive bridging faults, crosstalk faults and transient faults, and analysis of their effects in some circuits of interest
Design of basic components usually employed in high reliability systems and their prototyping by means of FPGA
Bibliography
J. Segura C. F. Hawkins, “CMOS Electronics – How It Works, How It Fails” IEEE Press – Wiley, 2004.
M. L. Bushnell, V. D. Agrawal, “Essential of Electronic Testing”, Kluwer Academic Publishers, 2000
M. Abramovici, M. A. Bruer, A. D. Friedman, “Digital Systems Testing and Testable Design”, Computer Science Press, 1990
S. Mourad, Y. Zorian, “Principles of Testing Electronic Systems”, Essential of Electronic Testing”,Wiley, 2000
N. K. Jha, S. Kundu, “Testing and Reliable Design of CMOS Circuits”, Kluwer Academic Publishers, 1990
P. K. Lala, “Self-Checking and Fault Tolerant Digital Design”, Morgan Caufmann Publ, 2001
Teaching methods
Lessons and computer practice
